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NLAS4684 Ultra-Low Resistance Dual SPDT Analog Switch
The NLAS4684 is an advanced CMOS analog switch fabricated in Sub-micron silicon gate CMOS technology. The device is a dual Independent Single Pole Double Throw (SPDT) switch featuring Ultra-Low RON of 0.5 W, for the Normally Closed (NC) switch, and 0.8 W for the Normally Opened switch (NO) at 2.7 V. The part also features guaranteed Break Before Make switching, assuring the switches never short the driver. The NLAS4684 is available in a 2.0 x 1.5 mm bumped die array. The pitch of the solder bumps is 0.5 mm for easy handling.
Features http://onsemi.com MARKING DIAGRAMS
* Ultra-Low RON, t0.5 W at 2.7 V * Threshold Adjusted to Function with 1.8 V Control at * * * * * * * * * * * * * * * * *
VCC = 2.7-3.3 V Single Supply Operation from 1.8-5.5 V Tiny 2 x 1.5 mm Bumped Die Low Crosstalk, t 83 dB at 100 kHz Full 0-VCC Signal Handling Capability High Isolation, -65 dB at 100 kHz Low Standby Current, t50 nA Low Distortion, t0.14% THD RON Flatness of 0.15 W Pin for Pin Replacement for MAX4684 High Continuous Current Capability $300 mA Through Each Switch Large Current Clamping Diodes at Analog Inputs $300 mA Continuous Current Capability Pb-Free Packages are Available Cell Phone Speaker Switching Power Switching Modems Automotive
A1 Microbump-10 CASE 489AA A1
4684 AYWWG G
1 1 QFN-10 CASE 485C
NLAS 4684 ALYWG G
1 Micro10 CASE 846B
4684 AYWG G
Applications
A = Assembly Location L = Wafer Lot Y = Year WW, W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
FUNCTION TABLE
IN 1, 2 0 1 NO 1, 2 OFF ON NC 1, 2 ON OFF
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
January, 2007 - Rev. 15
Publication Order Number: NLAS4684/D
NLAS4684
GND NC2 IN2 COM2
6 7 8 9
5 NC1 4 IN1 3 COM1 2 NO1 1 VCC (Top View)
NO2 10
Figure 1. Pin Connections and Logic Diagram (QFN-10 and Micro10)
GND B1 NC1 C1 A1 NC2
IN1 COM1 NO1
C2 C3 C4 B4 VCC (Top View)
A2 A3 A4
IN2 COM2 NO2
Figure 2. Pin Connections and Logic Diagram (Microbump-10)
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NLAS4684
MAXIMUM RATINGS
Symbol VCC VIS VIN Ianl1 Ianl-pk 1 Iclmp Iclmp 1 Positive DC Supply Voltage Analog Input Voltage (VNO, VNC, or VCOM) Digital Select Input Voltage Continuous DC Current from COM to NC/NO Peak Current from COM to NC/NO, 10 duty cycle (Note 1) Continuous DC Current into COM/NO/NC Peak Current into Input Clamp Diodes at COM/NC/NO Parameter Value *0.5 to )7.0 *0.5 v VIS v VCC )0.5 *0.5 v VI v)7.0 $300 $500 $300 $500 Unit V V V mA mA mA mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Defined as 10% ON, 90% off duty cycle.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VIS TA tr, tf DC Supply Voltage Digital Select Input Voltage Analog Input Voltage (NC, NO, COM) Operating Temperature Range Input Rise or Fall Time, SELECT VCC = 3.3 V $ 0.3 V VCC = 5.0 V $ 0.5 V Parameter Min 1.8 GND GND *55 0 0 Max 5.5 5.5 VCC )125 100 20 Unit V V V C ns/V
DC CHARACTERISTICS - Digital Section (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage, Select Inputs (Figure 10) Condition VCC $10% 2.0 2.5 3.0 5.0 2.0 2.5 3.0 5.0 VIN = 5.5 V or GND VIN = 5.5 V or GND Select and VIS = VCC or GND 5.5 0 5.5 *555C to 255C 1.4 1.4 1.4 2.0 0.5 0.5 0.5 0.8 $ 1.0 $10 $ 180 t855C 1.4 1.4 1.4 2.0 0.5 0.5 0.5 0.8 $ 1.0 $10 $ 200 t1255C 1.4 1.4 1.4 2.0 0.5 0.5 0.5 0.8 $ 1.0 $10 $ 200 Unit V
VIL
Maximum Low-Level Input Voltage, Select Inputs (Figure 10)
V
IIN IOFF ICC
Maximum Input Leakage Current, Select Inputs Power Off Leakage Current Maximum Quiescent Supply Current (Note 2)
mA mA nA
2. Guaranteed by design.
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NLAS4684
DC ELECTRICAL CHARACTERISTICS - Analog Section
Guaranteed Maximum Limit -555C to 255C Symbol RON (NC) Parameter NC "ON" Resistance (Note 3) Condition VIN v VIL VIS = GND to VCC IINI v 100 mA VIN w VIH VIS = GND to VCC IINI v 100 mA ICOM = 100 mA VIS = 0 to VCC ICOM = 100 mA VIS = 0 to VCC VIS = 1.3 V; ICOM = 100 mA VIS = 1.5 V; ICOM = 100 mA VIS = 2.8 V; ICOM = 100 mA VIN = VIL or VIH VNO or VNC = 1.0 VCOM = 4.5 V VIN = VIL or VIH VNO 1.0 V or 4.5 V with VNC floating or VNC 1.0 V or 4.5 V with VNO floating VCOM = 1.0 V or 4.5 V VCC $10% 2.5 3.0 5.0 2.5 3.0 5.0 2.5 3.0 5.0 2.5 3.0 5.0 2.5 3.0 5.0 5.5 -1 Min Max 0.6 0.5 0.4 1.0 0.8 0.8 0.15 0.15 0.15 0.35 0.35 0.35 0.18 0.06 0.06 1 -10 t855C Min Max 0.7 0.5 0.4 1.0 0.8 0.8 0.15 0.15 0.15 0.35 0.35 0.35 0.18 0.06 0.06 10 -100 t1255C Min Max 0.8 0.5 0.5 1.0 1.0 0.9 0.15 0.15 0.15 0.35 0.35 0.35 0.18 0.06 0.06 100 nA Unit W
RON (NO)
NO "ON" Resistance (Note 3)
W
RFLAT (NC)
NC_On-Resistance Flatness (Notes 3, 5)
W
RFLAT (NO)
NO_On-Resistance Flatness (Notes 3, 5)
W
DRON
On-Resistance Match Between Channels (Notes 3 and 4)
W
INC(OFF) INO(OFF) ICOM(ON)
NC or NO Off Leakage Current (Figure 13) (Note 3) COM ON Leakage Current (Figure 13) (Note 3)
5.5
-2
2
-20
20
-200
200
nA
3. Guaranteed by design. Resistance measurements do not include test circuit or package resistance. 4. DRON = RON(MAX) - RON(MIN) between NC1 and NC2 or between NO1 and NO2. 5. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges.
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NLAS4684
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) (Typical characteristics are at 25C)
Guaranteed Maximum Limit VCC (V) 2.5 3.0 5.0 2.5 3.0 5.0 3.0 VIS (V) 1.3 1.5 2.8 1.3 1.5 2.8 1.5 2 15 *555C to 255C Min Typ Max 60 50 30 50 40 30 t855C Min Max 70 60 35 55 50 35 t1255C Min Max 70 60 35 55 50 35 Unit ns
Symbol tON
Parameter Turn-On Time
Test Conditions RL = 50 W, CL = 35 pF (Figures 4 and 5)
tOFF
Turn-Off Time
RL = 50 W, CL = 35 pF (Figures 4 and 5)
ns
tBBM
Minimum Break-Before-Make Time (Note 6)
VIS = 3.0 RL = 300 W, CL = 35 pF (Figure 3)
ns
Typical @ 25, VCC = 5.0 V CNC Off CNO Off CNC On CNO On NC Off Capacitance, f = 1 MHz NO Off Capacitance, f = 1 MHz NC On Capacitance, f = 1 MHz NO On Capacitance, f = 1 MHz 102 104 322 330 pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol BW Parameter Maximum On-Channel -3dB Bandwidth or Minimum Frequency Response Maximum Feed-through On Loss Off-Channel Isolation (Note 7) Charge Injection Select Input to Common I/O (Figures 10 and 11) Total Harmonic Distortion THD + Noise (Figure 9) Channel-to-Channel Crosstalk Condition VIN = 0 dBm VIN centered between VCC and GND (Figure 6) VIN = 0 dBm @ 100 kHz to 50 MHz VIN centered between VCC and GND (Figure 6) f = 100 kHz; VIS = 1 V RMS; CL = 5 nF VIN centered between VCC and GND(Figure 6) VIN = VCC to GND, RIS = 0 W, CL = 1 nF Q = CL - DVOUT (Figure 7) FIS = 20 Hz to 100 kHz, RL = Rgen = 600 W, CL = 50 pF VIS = 1 V RMS f = 100 kHz; VIS = 1 V RMS, CL = 5 pF, RL = 50 W VIN centered between VCC and GND (Figure 6) NC NO VCC V 3.0 3.0 3.0 3.0 3.0 3.0 3.0 Typical 255C 6.5 9.5 -0.05 -65 15 0.14 -83 pC % dB dB dB Unit MHz
VONL VISO Q THD VCT
6. -55C specifications are guaranteed by design. 7. Off-Channel Isolation = 20log10 (Vcom/Vno) (See Figure 6).
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NLAS4684
DUT VCC 0.1 mF 50 W Output VOUT 35 pF 90% Output Input GND tBMM 90% of VOH VCC
Switch Select Pin GND
Figure 3. tBBM (Time Break-Before-Make)
VCC DUT VCC 0.1 mF Open Output VOUT 50 W 35 pF Output VOL Input tON tOFF Input 0V VOH 90% 90% 50% 50%
Figure 4. tON/tOFF
VCC DUT Output Open 50 W VOUT 35 pF Input
VCC 50% 0V VOH Output VOL 10% 10% 50%
Input
tOFF
tON
Figure 5. tON/tOFF
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NLAS4684
50 W Reference Input Output 50 W Generator 50 W DUT Transmitted
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. VISO = Off Channel Isolation = 20 Log VONL = On Channel Loss = 20 Log VOUT VIN for VIN at 100 kHz
VOUT VIN
for VIN at 100 kHz to 50 MHz
Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 W
Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL
DUT Open Output VIN
VCC GND CL Output Off Off DVOUT
VIN
On
Figure 7. Charge Injection: (Q)
10
1 THD (%)
NC1 0.1 NO1
0.01 1 10 100 1000 10000 100000 FREQUENCY (Hz)
Figure 8. Total Harmonic Distortion Plus Noise Versus Frequency
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NLAS4684
1.6 200
CHARGE INJECTION "Q" (pC)
1.4 CURRENT LEAKAGE (nA) 1.2 1 0.8 0.6 0.4 0.2 0 0 2 VCC (V) 4 6 Threshold Rising Threshold Falling
NO, VCC = 5 V 0 NC, VCC = 5 V
-200
-400
-600
-800 0
2 Vin (V)
4
6
Figure 9. Voltage in Threshold on Logic Pins
Figure 10. Charge Injection versus Vis
70 60 T-on 2.5 V T-on / T-off (ns)
100 90 80 T-on / T-off (ns) 70 60 50 40 30 20 T-off T-on
50 T-off 2.5 V 40 30 20 10 0 -55 T-on 3.0 V T-off 3.0 V T-on 5.0 V
T-off 5.0 V
10 -30 -5 20 45 70 95 120 0 1.8 2.8 3.8 4.8
TEMPERATURE (C)
VCC TEMPERATURE (C)
Figure 11. T-on / T-off Time versus Temperature
Figure 12. T-on / T-off Time versus Temperature
1000 NO/NC CURRENT LEAKAGE (nA) 100 10 1 0.1 Open Switch 0.01 Comm / Closed Switch
1000 ICC CURRENT LEAKAGE (nA) 100 10 1 0.1 0.01
0.001 -55
-5
45
95
0.001 -55
-5
45
95
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. NO/NC Current Leakage Off and On, VCC = 5 V http://onsemi.com
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Figure 14. ICC Current Leakage versus Temperature VCC = 5.5 V
NLAS4684
3 1.8 V 2.5 2 2.0 V RON (W) RON (W) 1.5 1 0.5 0 0.0 1.0 2.0 3.0 4.0 5.0 VCOM (V) 2.3 V 2.5 V 2.7 V 3.0 V 5.0 V 2.5 2 1.5 1 0.5 0 0.0 1.0 2.0 3.0 4.0 5.0 2.3 V 2.5 V 3.0 V 5.0 V 2.7 V TA = +25C ICOM = 100 mA 4.5 1.8 V 4 3.5 3 2.0 V TA = +25C ICOM = 100 mA
VCOM (V)
Figure 15. NC On-Resistance versus COM Voltage
Figure 16. NO On-Resistance versus COM Voltage
0.45 0.4 0.35 RON (W) 0.3 0.25 0.2 -40C 0.15 0.1 0.0 +25C +85C VCC = 2.5 V ICOM = 100 mA
1.3 1.1 0.9 RON (W) 0.7 0.5 0.3 0.1 0.0 1.0 2.0 VCOM (V) 3.0 4.0 5.0 -40C VCC = 2.5 V ICOM = 100 mA +85C +25C
0.5
1.0 VCOM (V)
1.5
2.0
2.5
Figure 17. NC On-Resistance versus COM Voltage
0.35 0.9 0.8 0.3 AVERAGE RON (W) +85C AVERAGE RON (W) +25C 0.25 -40C 0.2 0.7
Figure 18. NO On-Resistance versus COM Voltage
+85C +25C
-40C 0.6 0.5 0.4 0.3 0.2 VCC = 3 V ICOM = 100 mA 1.0 VCOM (V) 2.0 3.0
0.15 VCC = 3 V ICOM = 100 mA 0.1 0.0 1.0 VCOM (V) 2.0 3.0
0.1 0.0
Figure 19. NC On-Resistance versus COM Voltage
Figure 20. NC On-Resistance versus COM Voltage
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NLAS4684
0.26 0.24 -40C AVERAGE RON (W) 0.2 0.18 0.16 0.14 0.12 0.1 0.0 1.0 2.0 VCOM (V) 3.0 4.0 5.0 VCC = 5 V ICOM = 100 mA +85C AVERAGE RON (W) 0.22 +25C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 VCC = 5 V ICOM = 100 mA 1.0 2.0 VCOM (V) 3.0 4.0 5.0 -40C 0.9 0.8 +85C +25C
Figure 21. NC On-Resistance versus COM Voltage
Figure 22. NO On-Resistance versus COM Voltage
0 PHASE (Degrees) BANDWIDTH (dB/Div) -1 BANDWIDTH (dB/Div) Bandwidth (On - Loss)
0 -1 Bandwidth (On - Loss) PHASE (Degrees)
10 0 Phase Shift (Degrees)
10 0 Phase Shift (Degrees)
-10
-10
-10 0.001
VCC = 3.0 V TA = 25C 0.01 0.1 1.0 10 100
-10 0.001
VCC = 3.0 V TA = 25C 0.01 0.1 1.0 10 100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. NC Bandwidth and Phase Shift versus Frequency
Figure 24. NO Bandwidth and Phase Shift versus Frequency
0 -10 NC Off-Isolation
0 -10 NO Off-Isolation
Crosstalk
Crosstalk
VCC = 3.0 V TA = 25C -100 0.001 0.01 0.1 1.0 10 100 -100 0.001 0.01 0.1 1.0
VCC = 3.0 V TA = 25C 10 100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. NC Off Isolation and Crosstalk
Figure 26. NO Off Isolation and Crosstalk
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NLAS4684
ORDERING INFORMATION
Device NLAS4684FCT1 NLAS4684FCT1G NLAS4684MNR2 NLAS4684MNR2G NLAS4684MR2 NLAS4684MR2G Package Microbump-10 Microbump-10 (Pb-Free) QFN-10 QFN-10 (Pb-Free) Micro10 Micro10 (Pb-Free) Shipping 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel 4000 / Tape & Reel 4000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NLAS4684
PACKAGE DIMENSIONS
Microbump-10 CASE 489AA-01 ISSUE A
4X
D 0.10 C
PIN ONE CORNER
A
B
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. MILLIMETERS DIM MIN MAX A --- 0.650 A1 0.210 0.270 A2 0.280 0.380 D 1.965 BSC E 1.465 BSC b 0.250 0.350 e 0.500 BSC D1 1.500 BSC E1 1.000 BSC
A1 0.10 C A2 0.075 C A C
SEATING PLANE
D1 e
10 X
b
C B A 1 2 3 4
0.15 C A B 0.05 C
E1 e
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NLAS4684
PACKAGE DIMENSIONS
DFN10, 3 x 3mm, 0.5mm Pitch CASE 485C-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.45 2.55 3.00 BSC 1.75 1.85 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03
EDGE OF PACKAGE
E
L1 DETAIL A Bottom View (Optional)
PIN 1 REFERENCE 2X 2X
0.15 C
0.15 C 0.10 C
10X
0.08 C SIDE VIEW A1 C
1
5
A1 E2
10X
K
10 10X
6
b BOTTOM VIEW
0.10 C A B 0.05 C
NOTE 3
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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EE EE EE
10X
L
CCCC CCCC CCCC
DETAIL B
TOP VIEW
(A3) A
SEATING PLANE
EXPOSED Cu
D2 e
DETAIL A
MOLD CMPD
A3
DETAIL B Side View (Optional)
SOLDERING FOOTPRINT*
2.6016
2.1746
1.8508
3.3048
10X
0.5651
10X
0.3008
0.5000 PITCH
DIMENSIONS: MILLIMETERS
NLAS4684
PACKAGE DIMENSIONS
Micro10 CASE 846B-03 ISSUE D
-A-
K
-B-
PIN 1 ID
G
D 8 PL 0.08 (0.003)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION "A" DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION "B" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B-01 OBSOLETE. NEW STANDARD 846B-02 DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.30 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.012 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028
M
TB
S
A
S
0.038 (0.0015) -T- SEATING
PLANE
C H J L
SOLDERING FOOTPRINT*
10X
1.04 0.041
0.32 0.0126
10X
3.20 0.126
4.24 0.167
5.28 0.208
8X
0.50 0.0196
SCALE 8:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NLAS4684/D

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